This invention relates to test systems for complex VLSI (Very Large Scale Integrated) circuit chips found in the state of the art digital electronics system. In particular, this invention relates to special test and diagnostic circuitry that resides on or is embedded in a VLSI chip together with the circuitry which performs the specified chip function. This test and diagnostic circuitry may be used for initial testing of the chip or testing at any time during the useful life of the chip and may include testing of the electronic system in which the chip resides. The flexible embedded test system is sometimes known as FITS.
Known in the prior art is U.S. Pat. No. 4,357,703 entitled "Test System for LSI Circuits Resident on LSI Chips." This patent shows a test system which has switchable gates for controlling internal data flow at the input and output of the logic, shift registers for serially receiving data and transmitting data in parallel and a test generator and receiver system. In practice, this system has been very useful in logic design. However, as VLSI logic gets more complex with an ever increasing number of gates on a chip, design and testing needs to become more sophisticated. The design in this patent does not provide adequate ability to look backward in the chip logic sequence from the output register to find the source of transient and intermittent faults. Thus, there is a need to provide for improved detection and isolation of error conditions within chip logic circuitry.
Also known in the prior art is U.S. Pat. No. 4,244,048 entitled "Chip and Wafer Configuration and Testing Method for Large Scale Integrated Circuits." This patent shows a scan design chip testing method which can be implemented both on individual chips and also on a wafer containing a number of chips during fabrication. This patent shows implementation of scan design technology which reduced to simplest terms refers to the ability of a register or a rank of flip-flops to serially scan data into and out of the rank for testing purposes but which normally conveys data in a parallel fashion from one stage of combinational logic to another stage of combinational logic. A chip having scan design can allow the entire chip contents or only selected operands to be read in or out. However, with scan design, the entire scan data path must be accessed every time it is used including portions which may not be of interest. All of this serial transfer of a one bit wide data path takes a lot of time.
As logic chips become larger and larger, the difficulty of using a scan design increases because of the number of control signals required and the number of bits contained in all of the flip-flop or register ranks on a large chip. These make the testing or diagnostic overhead sufficiently large that it becomes a problem in itself. For example, a large number of flip-flop bit sequences requires a very substantial data base of test operands and expected results. Similarly, each different chip type or design requires its own special testing and diagnostic sequences. Thus, while a scan design offers some advantages for determining the contents of the registers or flip-flops in a chip, it also has the burden of producing a cumbersome amount of data. Thus, there is a need to provide for a way of using the benefits of scan design but avoiding unnecessarily large data bases of test operands and for producing a more manageable chip testing routine.